The present invention relates to a bipolar transistor with a base region extending vertically to the surface of a semiconductor substrate and to a method for fabricating such a transistor.
A bipolar transistor operating at even higher speeds is in high demand to further improve the performance of a semi-conductor integrated circuit device.
Reduction in base-emitter or base-collector parasitic capacitance plays a key role in increasing the operating speed of a bipolar transistor. To minimize the parasitic capacitance, a junction region between the base and emitter regions or between the base and collector regions should preferably have its area reduced.
For that purpose, the base-emitter or base-collector junction region is formed by lithography according to a known technique to make its area as small as possible.
When the lithography technique is adopted, however, the precision of fine-line processing is dependent on the wavelength of radiation emitted from a light source for the lithographic process. In other words, it is difficult to define a fine-line pattern at a precision equal to or smaller than the wavelength of the radiation. Thus, the area of the junction region cannot be reduced below a certain limit.
Japanese Laid-Open Publication No. 5-182978 discloses an alternative method for reducing the base-emitter or base collector junction area.
Hereinafter, the method for fabricating a bipolar transistor as disclosed in the publication identified above will be described with reference to FIGS. 3(a) through 3(d).
First, as shown in FIG. 3(a), a silicon-on-insulator (SOI) substrate is prepared. In the SOI substrate, an n-type first single crystal silicon layer 102 is formed over a silicon substrate 100 with a first silicon dioxide film 101 interposed therebetween. Next, the first single crystal silicon layer 102 is selectively doped with As ions, thereby defining a collector connection region 103. In this case, the first single crystal silicon layer 102 will be a collector region. Then, a second silicon dioxide film 104 is deposited by a CVD process on the first single crystal silicon layer 102 and collector connection region 103, and a p-type first polysilicon layer 105 is deposited by a CVD process on the second silicon dioxide film 104.
Next, as shown in FIG. 3(b), an opening 106 is provided through the first polysilicon layer 105, second silicon dioxide film 104 and first single crystal silicon layer 102. The opening 106 is provided to form a transistor thereon. Subsequently, an epitaxy process is performed under the conditions so defined as to grow epitaxial and polysilicon layers at the same time. As a result of this process, a p-type second single crystal silicon layer 107 is formed on the side faces of the first single crystal silicon layer 102. Also, a p-type second polysilicon layer 108 is deposited to cover the upper and side faces of the first polysilicon layer 105, the side faces of the second silicon dioxide film 104 and the upper surface of the first silicon dioxide film 101. Then, the layers 107 and 108 are etched anisotropically, thereby leaving the p-type second single crystal silicon layer 107 on the side faces of the first single crystal silicon layer 102 and the second polysilicon layer 108 on the side faces of the first polysilicon layer 105 and second silicon dioxide film 104, respectively. The second single crystal silicon layer 107 will be an intrinsic base region, while the first and second polysilicon layers 105 and 108 will together constitute a base connection region.
Then, a resist pattern is defined over the entire surface of the first polysilicon layer 105 and then etched under controlled conditions, thereby partially leaving the resist pattern 109 inside the opening 106 where an emitter region will be defined as shown in FIG. 3(c). Subsequently, a third silicon dioxide film 110 is deposited on parts of the first and second polysilicon layers 105 and 108 that are not covered with the resist pattern 109.
Thereafter, as shown in FIG. 3(d), the resist pattern 109 is stripped. Then, an n-type third single crystal silicon layer 111 is formed on the side faces of the second single crystal silicon layer 107 (i.e., the exposed inner wall of the opening 106 that is not covered with the third silicon dioxide film 110). The third single crystal silicon layer 111 will be an emitter region. Subsequently, an n-type third polysilicon layer 112 is deposited over the entire surface of the third silicon dioxide film 110 as well as over the inner wall of the opening 106, and then patterned. The patterned third polysilicon layer 112 will be an emitter connection region.
Next, the third silicon dioxide film 110 and the first polysilicon layer 105 are patterned, and then the second silicon dioxide film 104 is patterned. Thereafter, openings are provided in the third silicon dioxide film 110 to form electrodes thereon. Subsequently, an aluminum film is deposited over the collector connection region 103, second and third silicon dioxide films 104, 110 and third polysilicon layer 112 and then patterned. As a result, emitter, base and collector electrodes 114A, 114B and 114C are formed to be connected to the third polysilicon layer 112, first polysilicon layer 105 and collector connection regions 103, respectively. In this manner, the prior art bipolar transistor is completed.
In the prior art bipolar transistor, the area of the junction between the first and second single crystal silicon layers 102 and 107 functioning as the collector and intrinsic base regions is defined by the thickness of the first single crystal silicon layer 102. Thus, the base-collector parasitic capacitance can be reduced if the first single crystal silicon layer 102 is thinned. Also, the area of the junction between the second and third single crystal silicon layers 107 and 111, which function as the intrinsic base and emitter regions, respectively, is defined by the height of the third single crystal silicon layer 111, or the thickness of the resist pattern 109 left inside the opening 106. Thus, the base-emitter parasitic capacitance can be reduced if the resist pattern 109 left within the opening 106 is thinned.
In the prior art bipolar transistor, however, it is difficult to precisely control the thickness of the resist pattern 109 left within the opening 106. This is because the resist pattern 109 is defined by etching the resist pattern that has been deposited over the entire surface of the first polysilicon layer 105 under controlled conditions.
For that reason, it is also difficult to precisely control the height of the third single crystal silicon layer 111, or the area of the base-emitter junction region. As a result, the base-emitter parasitic capacitance becomes variable, thus making the electrical characteristics of the bipolar transistor inconstant.